Quality Gate Control Theory: Real-Time Stability Analysis for Manufacturing AI

Abstract

Manufacturing environments present a fundamentally different governance challenge than software or financial decision systems. In software, a decision is either correct or incorrect at a discrete point in time. In manufacturing, quality is a continuous dynamical variable -- defect rates evolve over time, driven by material property fluctuations, tool wear accumulation, environmental temperature drift, and the interactions between hundreds of process parameters. A quality gate in manufacturing is not a binary pass/fail checkpoint; it is a feedback controller that must stabilize a continuous process against persistent disturbances.

This paper formalizes the manufacturing quality gate as a control system problem. We model the defect rate d(t) as a state variable in a dynamical system, derive the plant transfer function G(s) relating process inputs to defect outputs, and design a PID-style gate controller C(s) that maintains d(t) below a configurable tolerance d_max in the presence of bounded disturbances. We apply Lyapunov stability theory to prove that the closed-loop quality system has a globally asymptotically stable equilibrium at d* = 0 when the controller gains satisfy explicitly derived conditions. We then analyze disturbance rejection capability, showing that the gate controller provides bounded-input bounded-output (BIBO) stability and quantifying the worst-case defect excursion under material variation, tool wear, and environmental drift disturbances.

The analysis extends to multi-stage quality cascades -- sequential manufacturing steps where the output quality of one stage becomes the input quality of the next. We derive the cascade transfer function and show that properly tuned gates at each stage provide geometric attenuation of defect propagation, with an attenuation factor of 0.12x per stage in our experimental configuration.

We validate the framework on a semiconductor fabrication case study involving photolithography, etching, deposition, chemical-mechanical polishing, and metrology inspection. The PID gate controller achieves 94.7% defect containment (fraction of out-of-tolerance conditions caught before downstream propagation), with a mean gate response time of 178ms and a minimum gain margin of 8.3dB under worst-case material variation. The system is implemented as an extension of the MARIA OS Gate Engine, demonstrating that the same governance architecture used for software and financial decision gates can be extended to continuous manufacturing processes with appropriate control-theoretic foundations.

The core insight is that quality governance in manufacturing is a stability problem, not a classification problem. Gates must not merely detect defects -- they must stabilize the defect rate against disturbances, maintain stability margins against model uncertainty, and attenuate defect propagation through multi-stage processes. Control theory provides the mathematical framework to achieve these objectives with provable guarantees.

1. The Manufacturing Quality Crisis in AI-Driven Production

The integration of AI into manufacturing production lines has accelerated dramatically. AI-driven systems now control lithography alignment in semiconductor fabs, adjust welding parameters in automotive assembly, optimize chemical dosing in pharmaceutical production, and manage thermal profiles in additive manufacturing. These systems offer unprecedented throughput and precision -- but they introduce a governance challenge that existing quality frameworks were not designed to handle.

1.1 The Temporal Dimension of Manufacturing Quality

Traditional quality assurance in manufacturing relies on Statistical Process Control (SPC), which monitors process outputs against control limits derived from historical data. SPC is fundamentally a detection framework: it identifies when a process has drifted out of control and triggers corrective action. The limitation is latency. By the time an SPC chart signals an out-of-control condition, the defective products have already been produced. In high-volume manufacturing -- where a semiconductor fab produces thousands of wafers per day and each wafer contains billions of transistors -- even a few minutes of undetected drift can produce millions of defective components.

AI-driven process control promises to close this latency gap by predicting quality deviations before they occur and adjusting process parameters in real time. But this introduces a new problem: the AI controller is itself a source of instability. A controller that over-corrects creates oscillations. A controller that responds to noise as if it were signal introduces spurious variation. A controller that optimizes for one quality metric at the expense of others creates multi-dimensional drift. The quality gate must govern not only the manufacturing process but also the AI controller that manages it.

1.2 Failure Modes Unique to AI-Controlled Manufacturing

We identify four failure modes specific to AI-controlled manufacturing that traditional SPC does not address:

Mode 1 -- Controller oscillation: The AI controller adjusts a process parameter to correct a detected deviation. The correction overshoots, causing a deviation in the opposite direction. The controller corrects again, producing a growing oscillation. In semiconductor lithography, this manifests as alternating over-exposure and under-exposure across successive wafers, producing a bimodal defect distribution that SPC detects only after significant yield loss.

Mode 2 -- Noise amplification: The AI controller treats measurement noise as a real process deviation and adjusts accordingly. Each adjustment introduces real variation that was not present before the correction. This is the classic problem of responding to common-cause variation as if it were special-cause variation -- but AI controllers, lacking the statistical intuition of an experienced process engineer, are particularly susceptible.

Mode 3 -- Cross-parameter coupling: Manufacturing processes have complex parameter interactions. Adjusting temperature to correct a thickness deviation may shift the stress profile, which affects the subsequent etching rate, which produces a dimensional deviation two stages downstream. AI controllers optimizing a single parameter at a single stage can destabilize the entire multi-stage process.

Mode 4 -- Concept drift: The relationship between process parameters and quality outcomes changes over time due to equipment aging, material lot changes, and environmental variation. An AI controller trained on historical data gradually loses accuracy as the underlying process evolves. Without explicit drift detection, the controller's corrections become increasingly inappropriate, introducing systematic bias.

1.3 The Control Theory Imperative

These failure modes share a common structure: they are all stability problems. Controller oscillation is an instability in the feedback loop. Noise amplification is a failure of disturbance rejection. Cross-parameter coupling is an inadequate model of the plant dynamics. Concept drift is a time-varying system that the controller fails to track. Control theory provides a unified mathematical framework for analyzing and solving all four problems.

The key conceptual shift is to stop treating the quality gate as a checkpoint and start treating it as a controller. A checkpoint inspects a product and makes a binary decision: pass or fail. A controller observes the process state, computes a corrective signal, and adjusts the process in real time to maintain stability. The checkpoint is reactive; the controller is proactive. The checkpoint detects defects; the controller prevents them.

In the MARIA OS framework, this means extending the gate evaluation pipeline from a five-step classification process (risk scoring, evidence check, threshold comparison, gate application, human escalation) to a continuous feedback loop that runs at every measurement cycle. The gate still performs classification for discrete decisions (accept lot, reject lot, escalate to human), but between those discrete decisions, it runs a continuous controller that stabilizes the defect rate.

2. Defect Rate as Dynamic State Variable

We begin by formalizing the manufacturing quality system as a dynamical system with the defect rate as the primary state variable.

2.1 State Variable Definition

where Delta_t is the measurement window (typically 1-60 seconds in high-volume manufacturing). The defect rate d(t) is the manufacturing analog of the risk score S_i = I_i x R_i in the MARIA OS responsibility framework -- both are continuous quantities that gate decisions depend on.

2.2 Process Dynamics

The defect rate evolves according to the process dynamics -- the physical relationship between controllable inputs (temperatures, pressures, speeds, dosages), uncontrollable disturbances (material properties, ambient conditions, equipment state), and quality outputs (dimensions, surface properties, electrical characteristics). We model the process as a first-order linear time-invariant (LTI) system with the following state equation:

where tau_p is the process time constant (the time scale over which the process naturally responds to input changes), K_p is the process gain (the steady-state ratio of defect rate change to input change), u(t) is the control input (the gate's corrective signal, representing process parameter adjustments), and w(t) is the disturbance input (the combined effect of material variation, tool wear, and environmental drift).

The first-order model captures the essential dynamics: the process has inertia (characterized by tau_p), gain (K_p), and is subject to external disturbances (w(t)). While real manufacturing processes are higher-order and nonlinear, the first-order approximation is widely used in process control because it captures the dominant dynamic mode and provides a tractable basis for controller design.

2.3 Transfer Function Representation

Taking the Laplace transform of the state equation with zero initial conditions:

Rearranging:

The plant transfer function (from control input to defect rate) is:

This is a first-order lag with DC gain K_p and time constant tau_p. The disturbance transfer function (from disturbance to defect rate) is:

Both transfer functions share the same pole at s = -1/tau_p, confirming that the open-loop process is stable (the pole is in the left half-plane). However, open-loop stability does not mean the defect rate remains within tolerance -- it means the defect rate settles to a finite steady-state value for any bounded input. If the disturbance is persistent (e.g., a material lot change that shifts the process mean), the steady-state defect rate may exceed tolerance. The controller's job is to reject such disturbances.

2.4 State Space Augmentation

For the multi-stage analysis in Section 8, we augment the state vector to include the integral of the defect rate (for integral control) and the defect rates at upstream stages. The augmented state vector is:

where d_up(t) is the defect rate arriving from the upstream stage. The augmented state space model provides the foundation for the multi-stage cascade analysis.

2.5 Parameter Identification

The process parameters K_p and tau_p are identified from step response experiments. A known step change in a process parameter (e.g., a 5-degree temperature increase) is applied, and the resulting change in defect rate is measured over time. The DC gain K_p is the ratio of steady-state defect rate change to step input magnitude. The time constant tau_p is the time for the defect rate to reach 63.2% of its steady-state value.

In practice, K_p and tau_p vary with the operating point and change over time (due to equipment aging, recipe changes, etc.). The controller must be robust to these variations, which motivates the stability margin analysis in Section 5.

3. Control-Theoretic Gate Model

With the plant dynamics established, we now design the quality gate as a feedback controller. The gate observes the defect rate d(t), compares it to a reference (target defect rate d_ref, typically zero or a small acceptable baseline), computes an error signal, and generates a corrective control input u(t).

3.1 Feedback Loop Architecture

The standard feedback control architecture for the manufacturing quality gate is:

  d_ref ──(+)── e(t) ──> [ C(s) ] ──> u(t) ──> [ G_p(s) ] ──(+)──> d(t)
           (-)                                          ^
            |                                           |
            └────────────── [ H(s) ] <──────────────────┘
                                          w(t) ──> (+)

where d_ref is the reference (target) defect rate, e(t) = d_ref - d(t) is the error signal, C(s) is the gate controller transfer function, u(t) is the control input (process parameter adjustments), G_p(s) is the plant transfer function, H(s) is the sensor/measurement transfer function, and w(t) is the disturbance. In the simplest case, H(s) = 1 (perfect measurement). In practice, H(s) captures measurement delay and filtering.

3.2 Closed-Loop Transfer Functions

The closed-loop transfer function from reference to output is:

For perfect tracking, T(s) should equal 1 at low frequencies (the defect rate follows the reference). The closed-loop transfer function from disturbance to output is:

S(s) is the sensitivity function -- it quantifies how well the controller rejects disturbances. For good disturbance rejection, |S(j omega)| should be small at frequencies where disturbances have significant energy. The denominator 1 + C(s) G_p(s) H(s) is common to both transfer functions and is called the characteristic polynomial. The stability of the closed-loop system is determined entirely by the roots of 1 + C(s) G_p(s) H(s) = 0.

3.3 Loop Gain and Stability Margins

The loop gain is L(s) = C(s) G_p(s) H(s). The Nyquist stability criterion states that the closed-loop system is stable if and only if the Nyquist plot of L(j omega) does not encircle the critical point -1 + 0j. In practice, we quantify the distance from the critical point using two margins:

Gain Margin (GM): The factor by which the loop gain can be increased before the system becomes unstable. Formally, GM = 1 / |L(j omega_180)| where omega_180 is the frequency at which the phase of L(j omega) is -180 degrees. A gain margin of GM > 6dB (factor of 2) is the minimum for industrial control systems. We target GM > 8dB for manufacturing quality gates.

Phase Margin (PM): The additional phase lag that the loop can tolerate before instability. Formally, PM = 180 + angle(L(j omega_c)) where omega_c is the gain crossover frequency (where |L(j omega_c)| = 1). A phase margin of PM > 45 degrees is standard. We target PM > 50 degrees for quality gates to provide adequate damping against oscillation.

3.4 Design Specifications

The quality gate controller must satisfy the following specifications simultaneously:

• Stability: The closed-loop system must be asymptotically stable (all poles in the left half-plane).
• Disturbance rejection: The steady-state defect rate under a step disturbance of magnitude w_0 must satisfy d_ss < d_max (the maximum tolerable defect rate).
• Response time: The time for the defect rate to return to within 5% of steady-state after a disturbance step must be less than T_settle (the required settling time).
• Overshoot: The peak defect rate excursion above steady-state must be less than d_peak (the maximum allowable transient defect rate).
• Robustness: The gain margin must exceed GM_min = 8dB and the phase margin must exceed PM_min = 50 degrees.
• Control effort: The magnitude of the control input |u(t)| must remain within physically realizable bounds (process parameters have finite adjustment ranges).

These specifications translate directly into constraints on the controller transfer function C(s), which we design in Section 6 as a PID controller.

4. Lyapunov Stability Analysis for Quality Systems

While the transfer function analysis of Section 3 provides frequency-domain stability conditions, Lyapunov theory provides a complementary time-domain analysis that is particularly powerful for establishing global stability and for handling nonlinear extensions of the quality gate model.

4.1 Lyapunov's Direct Method

Theorem (Lyapunov). Consider the autonomous system dx/dt = f(x) with equilibrium at x = 0. If there exists a continuously differentiable function V(x) such that V(0) = 0, V(x) > 0 for all x != 0 (positive definite), and dV/dt = (partial V / partial x) f(x) < 0 for all x != 0 (negative definite along trajectories), then the equilibrium x = 0 is globally asymptotically stable.

The function V(x) is called a Lyapunov function and serves as a generalized energy function for the system. If V decreases along every trajectory, the system's 'energy' is always dissipating, and every trajectory must converge to the equilibrium.

4.2 Lyapunov Function for the Quality Gate System

For the quality gate closed-loop system, we define the state as the error vector x(t) = [e(t), integral of e(t)]^T where e(t) = d_ref - d(t) is the defect rate error and the integral term captures accumulated error. We propose the quadratic Lyapunov function:

where K_I > 0 is the integral gain of the PID controller (to be designed in Section 6). This Lyapunov function is positive definite because it is a sum of squared terms with positive coefficients.

4.3 Time Derivative Analysis

Computing the time derivative of V along the closed-loop trajectories:

Since e(t) = d_ref - d(t) and d_ref is constant, we have de/dt = -dd/dt. Substituting the closed-loop dynamics (with the PID controller from Section 6):

where K_P, K_I, K_D are the PID gains and w'(t) represents the disturbance contribution. Setting w'(t) = 0 (nominal analysis) and collecting terms:

4.4 Stability Conditions

For dV/dt to be negative definite, the following conditions must hold:

Condition 1 (Proportional stability):

This ensures that the first term -(1/tau_p + K_p K_P / tau_p) e(t)^2 is strictly negative for all e(t) != 0.

Condition 2 (Derivative damping):

The derivative gain must be positive (to provide damping) but not too large (to avoid introducing right-half-plane zeros that destabilize the system). The upper bound depends on the process parameters tau_p, K_p and the proportional gain K_P.

Condition 3 (Integral bound):

The integral gain must be positive (to eliminate steady-state error) but below a critical value that depends on the proportional gain and process parameters. Exceeding this bound causes the integral term to dominate, introducing oscillatory behavior that can destabilize the system.

Theorem (Quality Gate Stability). If the PID controller gains K_P, K_I, K_D satisfy Conditions 1-3 simultaneously, then the closed-loop quality gate system has a globally asymptotically stable equilibrium at d(t) = d_ref (zero defect error) under zero disturbance. Furthermore, the convergence rate is at least exponential with rate lambda_min = min(1/tau_p + K_p K_P / tau_p, K_I).

4.5 Physical Interpretation

The three stability conditions have direct physical interpretations in the manufacturing context:

Condition 1 says that the gate must always correct in the right direction -- when the defect rate is above target, the corrective action must reduce it. This seems obvious but is violated when the sign of K_p changes (process reversal), which can happen if an actuator is miscalibrated or a control valve is installed backwards.

Condition 2 says that the gate's predictive correction (derivative action) must be appropriately sized. Too much derivative action causes the gate to over-react to transient fluctuations, creating the noise amplification failure mode described in Section 1.2. Too little derivative action provides insufficient damping, allowing oscillations.

Condition 3 says that the gate's accumulated error correction (integral action) must not be too aggressive. Excessive integral action causes the controller to 'wind up' during sustained disturbances, producing large overshoots when the disturbance subsides. This is the integral windup problem, well-known in process control, and directly relevant to manufacturing quality gates where sustained material lot changes can cause prolonged error accumulation.

4.6 Lyapunov Function for the Nonlinear Case

Real manufacturing processes are nonlinear -- the relationship between process parameters and defect rate is not a constant gain K_p but a function K_p(d, u) that varies with the operating point. For the nonlinear case, we use a modified Lyapunov function:

This generalized Lyapunov function accounts for the state-dependent gain and ensures that the stability analysis holds locally around any operating point. The conditions for local asymptotic stability become: K_P > 0, K_D > 0, K_I > 0, and the local gain K_p(d) must maintain consistent sign (no zero crossings) in the operating region.

5. PID Gate Controller Design

The PID (Proportional-Integral-Derivative) controller is the workhorse of industrial process control, used in over 95% of industrial control loops. We design a PID gate controller for the manufacturing quality system and derive the gain tuning rules specific to quality gate applications.

5.1 Controller Transfer Function

The PID gate controller has the transfer function:

where K_P is the proportional gain (corrective action proportional to current error), K_I is the integral gain (corrective action proportional to accumulated error), and K_D is the derivative gain (corrective action proportional to rate of change of error).

In the manufacturing quality context, each term has a specific role:

• Proportional action (K_P e(t)): When the defect rate is above target by Delta_d, the controller immediately adjusts process parameters by K_P x Delta_d. This provides the primary corrective force. Higher K_P produces faster response but risks oscillation.
• Integral action (K_I integral of e(t)): When the defect rate has been persistently above target, the accumulated error drives an increasing corrective signal. This eliminates steady-state offset -- without integral action, a constant disturbance (e.g., a permanent material lot change) would leave a permanent defect rate offset. The integral action drives steady-state error to zero.
• Derivative action (K_D de/dt): When the defect rate is changing rapidly (e.g., increasing due to a sudden tool wear event), the derivative term anticipates the future error and applies early corrective action. This reduces overshoot and improves transient response.

5.2 Closed-Loop Characteristic Equation

Substituting C(s) and G_p(s) into the characteristic equation 1 + C(s) G_p(s) = 0 (assuming H(s) = 1):

Multiplying through by s(tau_p s + 1):

This is a second-order characteristic equation (the system order is reduced from third to second because one pole-zero cancellation occurs when the integral action's zero at s = 0 cancels the open-loop integrator). The Routh-Hurwitz stability conditions for this equation are:

These are necessary and sufficient conditions for closed-loop stability. The first condition says the effective inertia must be positive. The second says the effective damping must be positive. The third says the effective stiffness must be positive. All three are satisfied by the Lyapunov conditions derived in Section 4.

5.3 Natural Frequency and Damping Ratio

The characteristic equation can be written in standard second-order form:

where the natural frequency omega_n and damping ratio zeta are:

The natural frequency determines how fast the quality gate responds to defect rate deviations. The damping ratio determines how much oscillation occurs during the response. For quality gate applications, we target zeta in [0.6, 0.8] -- sufficiently damped to avoid oscillation but not so overdamped that the response is sluggish.

5.4 Gain Tuning for Quality Gates

We derive gain tuning rules specific to the manufacturing quality gate application. Given the design specifications from Section 3.4:

Step 1 -- Set omega_n from settling time requirement:

For a target settling time of T_settle = 30 seconds (typical for semiconductor processes) and damping ratio zeta = 0.7, this gives omega_n = 0.19 rad/s.

Step 2 -- Set K_P from disturbance rejection requirement:

The steady-state defect rate under a step disturbance of magnitude w_0 is d_ss = w_0 tau_p / (1 + K_p K_P). For d_ss < d_max, we need:

Step 3 -- Set K_I from omega_n and K_D from zeta:

From the natural frequency and damping ratio expressions:

Solving these simultaneously (the equations are coupled through K_D) yields explicit gain values as functions of the process parameters (K_p, tau_p) and design specifications (T_settle, zeta, d_max, w_0).

Step 4 -- Verify stability margins:

Compute the gain margin and phase margin of the designed controller using the loop gain L(s) = C(s) G_p(s). If GM < 8dB or PM < 50 degrees, reduce K_P (which increases both margins at the cost of slower disturbance rejection) and repeat Steps 2-4.

5.5 Anti-Windup Implementation

In practice, the control input u(t) is bounded by physical limits (process parameters have finite adjustment ranges). When the integral term accumulates beyond what the actuator can deliver, integral windup occurs -- the integral state grows unboundedly, and when the error finally reverses sign, the large integral state causes excessive overshoot.

We implement back-calculation anti-windup: when the computed control input u(t) exceeds the actuator limit u_max, the integral state is reduced by the amount of saturation:

where u_sat is the saturated (actual) control input, u_unsat is the unsaturated (desired) control input, and T_aw is the anti-windup time constant (typically set to T_aw = sqrt(T_I x T_D) where T_I = K_P/K_I and T_D = K_D/K_P). This prevents integral windup while preserving the steady-state error elimination property of integral action during normal operation.

5.6 Derivative Filtering

Pure derivative action amplifies high-frequency measurement noise. We implement the derivative term with a first-order low-pass filter:

where T_f = K_D / (N K_P) is the filter time constant and N is the filter coefficient (typically N = 8-20). This limits the derivative gain at high frequencies to K_D / T_f = N K_P, preventing noise amplification while preserving the derivative action at frequencies below 1/T_f.

6. Disturbance Rejection: Material Variation, Tool Wear, Environmental Drift

The quality gate controller must reject three primary classes of disturbances that are characteristic of manufacturing environments. Each class has a distinct frequency profile and requires different controller capabilities.

6.1 Disturbance Classification

Class 1 -- Material variation (step disturbance): When a new material lot is introduced to the production line, the process mean shifts abruptly. Material properties (purity, grain size, thickness uniformity) vary between lots in ways that affect the process outcome. The disturbance model is a step function: w_material(t) = w_0 x step(t - t_lot), where w_0 is the magnitude of the lot-to-lot variation and t_lot is the time of lot change.

Class 2 -- Tool wear (ramp disturbance): Manufacturing tools degrade gradually over time. A cutting tool loses sharpness, a polishing pad thins, a chemical bath depletes. The disturbance model is a ramp function: w_tool(t) = r x (t - t_0) for t > t_0, where r is the wear rate (defect rate increase per unit time) and t_0 is the time when wear begins to affect quality.

Class 3 -- Environmental drift (sinusoidal disturbance): Temperature, humidity, and vibration in the manufacturing environment fluctuate cyclically. Cleanroom temperature oscillates with the HVAC cycle. Floor vibration follows the building's structural resonance. The disturbance model is a sinusoid: w_env(t) = A sin(omega_env t + phi), where A is the amplitude, omega_env is the environmental oscillation frequency, and phi is the phase.

6.2 Step Disturbance Rejection (Material Variation)

For a step disturbance W(s) = w_0 / s, the defect rate response is:

The steady-state defect rate (by the Final Value Theorem) is:

With the PID controller, S(0) = 0 (because the integral action provides infinite loop gain at DC). Therefore d_ss = 0 -- the PID controller completely rejects step disturbances at steady state. The transient response, however, depends on the controller gains. The peak defect rate excursion (overshoot) is:

For zeta = 0.7 and typical process parameters, d_peak is approximately 0.046 x w_0 x tau_p. This means that a material lot change causing a 1% shift in defect rate (w_0 = 0.01) with tau_p = 60s produces a peak excursion of approximately 0.028% -- well within tolerance for most manufacturing processes.

6.3 Ramp Disturbance Rejection (Tool Wear)

For a ramp disturbance W(s) = r / s^2, the steady-state error is:

With a PID controller (which has one integrator in C(s)), the system is type-1 with respect to the disturbance input. The steady-state error to a ramp is:

This is finite and non-zero -- the PID controller cannot completely reject ramp disturbances. However, the error can be made arbitrarily small by increasing K_I (at the cost of reduced stability margin). For a typical tool wear rate of r = 0.001%/hour and K_I tuned per Section 5.4, the steady-state tracking error is less than 0.002%, which is acceptable for most applications.

To achieve zero steady-state error to ramp disturbances, one would need a double integrator (PII^2D controller), but this introduces significant stability challenges and is rarely warranted in practice. The more practical approach is to combine the PID controller with a tool wear predictor that estimates the wear state from historical data and applies feedforward compensation.

6.4 Sinusoidal Disturbance Rejection (Environmental Drift)

For a sinusoidal disturbance w(t) = A sin(omega_env t), the steady-state defect rate oscillation amplitude is:

The sensitivity function magnitude |S(j omega)| determines the attenuation (or amplification) of environmental disturbances at each frequency. At frequencies well below the controller bandwidth (omega_env << omega_c), |S(j omega_env)| is small and the controller effectively rejects the disturbance. At frequencies near the controller bandwidth (omega_env approximately omega_c), |S(j omega_env)| may exceed 1 -- the controller actually amplifies the disturbance. At frequencies well above the controller bandwidth (omega_env >> omega_c), |S(j omega_env)| approaches 1 and the disturbance passes through unattenuated.

The peak of the sensitivity function (the maximum sensitivity M_s = max |S(j omega)|) is a key robustness metric. We require M_s < 2.0 (6dB), which corresponds to a minimum distance of 0.5 from the critical point in the Nyquist plot. This ensures that no disturbance frequency is amplified by more than a factor of 2 through the feedback loop.

6.5 Combined Disturbance Profile

In practice, all three disturbance classes act simultaneously. The total disturbance is:

The superposition principle (valid for the linear system) guarantees that the total defect rate response is the sum of the individual responses. The worst-case defect rate excursion occurs when all three disturbances align constructively:

For the controller designed in Section 5, the worst-case defect rate under simultaneous disturbances remains below d_max = 0.5% with the parameter values from the semiconductor case study in Section 10.

6.6 BIBO Stability Guarantee

Theorem (BIBO Stability). If the closed-loop system has all poles in the open left half-plane (satisfied by the Lyapunov conditions of Section 4) and the disturbance w(t) is bounded (|w(t)| <= w_max for all t), then the defect rate d(t) is bounded:

where ||S||_infinity = sup_omega |S(j omega)| is the H-infinity norm of the sensitivity function and ||G_w||_infinity is the H-infinity norm of the disturbance transfer function. This provides a hard upper bound on the defect rate for any bounded disturbance, regardless of its frequency content or temporal structure.

For the designed controller, ||S||_infinity = 1.68 and ||G_w||_infinity = tau_p = 60s (the DC gain of the disturbance transfer function). With w_max = 0.001 (maximum instantaneous disturbance rate) and d_ref = 0, the BIBO bound is d(t) <= 0.101% for all time. This is the formal guarantee that the quality gate controller provides: no matter what disturbances the manufacturing process encounters (as long as they are bounded by w_max), the defect rate will never exceed 0.101%.

7. Multi-Stage Quality Cascade: Sequential Gates

Manufacturing processes are typically multi-stage: a raw material passes through a sequence of processing steps (e.g., lithography -> etching -> deposition -> polishing -> inspection), each of which can introduce defects. The output quality of one stage becomes the input quality of the next, creating a quality cascade.

7.1 Cascade Architecture

Consider a manufacturing line with M sequential stages, each with its own quality gate controller. At stage k (k = 1, 2, ..., M):

• The input defect rate is d_{k-1}(t) (the output of the previous stage, with d_0(t) being the raw material quality)
• The local disturbance is w_k(t) (the disturbance specific to stage k)
• The local controller is C_k(s) with PID gains (K_{P,k}, K_{I,k}, K_{D,k})
• The local plant is G_{p,k}(s) = K_{p,k} / (tau_{p,k} s + 1)
• The output defect rate is d_k(t)

The dynamics at each stage are:

7.2 Cascade Transfer Function

In the Laplace domain, the defect rate at stage k depends on both the local disturbance and the upstream propagation:

where S_k(s) is the local sensitivity function (disturbance rejection at stage k), T_k(s) is the local complementary sensitivity function (input tracking at stage k), and alpha_k in [0, 1] is the defect coupling coefficient -- the fraction of upstream defects that propagate to stage k (some defects are corrected or become irrelevant at downstream stages).

The total defect rate at the final stage M is obtained by recursive substitution:

The first term is the sum of locally generated defects, each attenuated by the cascade of downstream gates. The second term is the raw material defects propagated through all stages.

7.3 Geometric Attenuation

If all stages have identical controllers (C_k = C for all k) and identical plants (G_{p,k} = G_p for all k), the defect propagation through the cascade simplifies. The attenuation per stage is:

where alpha is the (uniform) coupling coefficient and T(s) is the (common) complementary sensitivity function. For the designed controller with alpha = 0.3 (typical for semiconductor processes where not all defect types propagate) and |T(j omega)| <= 1.2 (slight peaking near the crossover frequency), the attenuation factor is:

However, with stage-specific gain optimization (where each stage has higher gain than its predecessor to compensate for accumulated upstream defects), we achieve an effective attenuation of eta = 0.12 per stage. After M = 5 stages, the raw material defect rate is attenuated by:

This means that defects in the raw material are reduced by a factor of approximately 40,000 through the 5-stage cascade -- each quality gate contributes multiplicatively to the overall defect reduction.

7.4 Cascade Stability Conditions

The cascade system is stable if and only if every individual stage is stable (because the stages are connected in series, and the series connection of stable systems is stable). However, the cascade introduces an additional concern: defect accumulation.

Even if each stage is locally stable, the total defect rate at the final stage is the sum of contributions from all stages. If each stage contributes a steady-state defect rate of d_ss,k (from its local disturbance), the total is:

For geometric attenuation (eta < 1), this sum converges, and the total defect rate is bounded. The practical condition is that the local defect contribution at the final stage (d_ss,M) dominates the total, because all upstream contributions are geometrically attenuated.

7.5 Inter-Stage Communication

In the MARIA OS implementation, quality gates at adjacent stages share information about the defect state. Stage k communicates its current defect rate d_k(t) and control action u_k(t) to stage k+1, enabling feedforward compensation. When stage k detects a disturbance and applies a corrective action, stage k+1 anticipates the propagated effect and adjusts proactively rather than waiting for the defect to appear in its own measurements.

The feedforward transfer function at stage k+1 is:

This ideal feedforward perfectly cancels the upstream defect propagation. In practice, model uncertainty limits the achievable cancellation, but even imperfect feedforward significantly reduces the transient defect excursion at downstream stages.

8. Integration with MARIA OS Gate Engine

The control-theoretic quality gate extends the MARIA OS Responsibility Gate Engine from discrete decision governance to continuous process governance. This section describes the architectural integration.

8.1 Dual-Mode Gate Operation

The MARIA OS quality gate operates in two modes simultaneously:

Continuous mode (PID controller): The gate runs the PID controller at every measurement cycle (typically 1-10 Hz in manufacturing). The controller reads the current defect rate from inline metrology sensors, computes the error against the target, evaluates the PID control law, and outputs corrective process parameter adjustments. This mode operates autonomously without human involvement for disturbances within the controller's rejection capability.

Discrete mode (fail-closed gate): The gate evaluates discrete decisions using the standard MARIA OS gate pipeline (risk scoring, evidence check, threshold comparison, human escalation). Discrete decisions include: accept/reject a production lot, change a process recipe, authorize a tool maintenance action, or escalate to a human process engineer. The discrete mode activates when the continuous controller encounters a condition it cannot handle -- a disturbance larger than the BIBO bound, a process parameter hitting its physical limit, or a model uncertainty indicator exceeding its threshold.

8.2 Escalation Triggers

The continuous controller escalates to the discrete gate (and potentially to human review) under four conditions:

Trigger 1 -- Defect exceedance: d(t) > d_max for more than T_hold seconds continuously. The controller has failed to bring the defect rate below tolerance within the expected settling time, indicating a disturbance larger than the design envelope.

Trigger 2 -- Control saturation: |u(t)| = u_max for more than T_sat seconds. The controller is at its actuator limit and cannot increase the corrective action. This indicates that the required correction exceeds the physical capability of the process adjustments.

Trigger 3 -- Oscillation detection: The defect rate has crossed the setpoint more than N_cross times in the last T_osc seconds. This indicates that the controller is oscillating, possibly due to a change in process dynamics that has reduced the stability margins below acceptable levels.

Trigger 4 -- Model divergence: The predicted defect rate (from the controller's internal model) diverges from the measured defect rate by more than delta_model for more than T_div seconds. This indicates that the plant model used for controller design is no longer accurate, and the controller gains may need to be retuned.

8.3 MARIA Coordinate Mapping

Manufacturing quality gates map to the MARIA Coordinate System as follows:

Galaxy (Enterprise)  -->  Manufacturing Company
  Universe (BU)      -->  Fab / Factory
    Planet (Domain)   -->  Product Line
      Zone (Ops)      -->  Process Stage (e.g., lithography, etching)
        Agent          -->  Quality Gate Controller at that stage

Each quality gate controller is an Agent in the MARIA coordinate system, with all the standard capabilities: risk scoring, evidence collection, audit logging, human escalation, and hierarchical policy inheritance. The process-specific parameters (K_p, tau_p, PID gains, disturbance bounds) are configured at the Zone level, while global policies (d_max, stability margin requirements, escalation SLAs) are set at the Planet or Universe level.

8.4 Evidence Bundle for Manufacturing

The evidence bundle for a manufacturing quality gate decision extends the standard MARIA OS evidence structure with process-specific fields:

• Metrology data: Inline measurement values (film thickness, critical dimension, overlay, resistivity) with timestamps and measurement uncertainty
• SPC chart state: Current control chart status (in-control, warning, out-of-control) with run test results
• Controller state: Current PID output, integral state, derivative estimate, and anti-windup status
• Disturbance estimate: Current estimated disturbance magnitude and classification (material, tool wear, environmental)
• Stability margins: Current gain margin and phase margin, computed from the latest plant model estimate
• Upstream defect state: Defect rates and controller states at upstream stages in the cascade

This evidence bundle enables human process engineers to make informed decisions when the gate escalates. Instead of receiving a bare 'defect rate exceeded' alert, the engineer sees the full dynamic state of the quality system, including what corrective actions have already been attempted and why they were insufficient.

8.5 Decision Pipeline Integration

Manufacturing quality gate decisions flow through the standard MARIA OS decision pipeline:

proposed (controller detects condition)
  --> validated (evidence bundle assembled, risk scored)
    --> approval_required (if escalation triggered)
      --> approved (human engineer authorizes action)
        --> executed (process parameter adjusted or lot dispositioned)
          --> completed/failed (outcome verified by subsequent metrology)

Every transition creates an immutable audit record. The entire control history -- every PID output, every escalation trigger, every human decision -- is recorded in the decision log. This provides the traceability required by quality management systems (ISO 9001, IATF 16949, AS9100) and semiconductor-specific standards (SEMI E10, SEMI E79).

9. Case Study: Semiconductor Manufacturing

We apply the control-theoretic quality gate framework to a semiconductor fabrication process involving five sequential stages. Semiconductor manufacturing is an ideal testbed because it combines high-volume production, tight tolerances, multi-stage processing, and significant process variability.

9.1 Process Description

The five-stage process consists of:

Stage 1 -- Photolithography: A photoresist layer is exposed to UV light through a patterned mask, transferring the circuit pattern to the wafer. The critical quality parameters are critical dimension (CD) and overlay accuracy. The primary disturbance is resist thickness variation between wafers (material variation, step disturbance).

Stage 2 -- Plasma etching: The exposed areas are removed by reactive ion etching (RIE). The critical quality parameters are etch depth, sidewall angle, and selectivity. The primary disturbance is etch rate drift due to chamber conditioning (tool wear, ramp disturbance).

Stage 3 -- Thin film deposition (CVD): A thin film of material (e.g., silicon dioxide, silicon nitride) is deposited on the wafer surface. The critical quality parameters are film thickness uniformity and composition. The primary disturbance is precursor gas flow variation (environmental, sinusoidal with HVAC cycle).

Stage 4 -- Chemical-Mechanical Polishing (CMP): The wafer surface is planarized by a combination of chemical dissolution and mechanical abrasion. The critical quality parameters are surface roughness and planarity. The primary disturbance is pad wear (tool wear, ramp) and slurry concentration variation (material, step).

Stage 5 -- Metrology/Inspection: The wafer is measured using optical, electron beam, and electrical test methods. This stage does not modify the wafer but provides the quality measurements that drive the upstream controllers. The primary challenge is measurement uncertainty, which adds noise to the feedback signal.

9.2 Process Parameters

The identified process parameters for each stage are:

| Stage | K_p | tau_p (s) | w_0 (step) | r (ramp, /hr) | A (sinusoid) | omega_env (rad/s) |

|---|---|---|---|---|---|---|

| Lithography | 0.15 | 45 | 0.008 | 0.0002 | 0.003 | 0.052 |

| Etching | 0.22 | 60 | 0.005 | 0.0008 | 0.002 | 0.052 |

| Deposition | 0.18 | 90 | 0.006 | 0.0003 | 0.005 | 0.105 |

| CMP | 0.25 | 30 | 0.010 | 0.0012 | 0.004 | 0.052 |

| Metrology | N/A | N/A | N/A | N/A | N/A | N/A |

Metrology (Stage 5) is a measurement-only stage with no controllable process parameters. The defect coupling coefficients between stages are alpha_12 = 0.35, alpha_23 = 0.28, alpha_34 = 0.22, alpha_45 = 0.15 (decreasing because later stages have less coupling to upstream defects).

9.3 Controller Design

Using the tuning rules from Section 5.4 with target specifications T_settle = 30s, zeta = 0.7, d_max = 0.5%, GM_min = 8dB, PM_min = 50 degrees:

| Stage | K_P | K_I | K_D | GM (dB) | PM (deg) | omega_n (rad/s) |

|---|---|---|---|---|---|---|

| Lithography | 18.2 | 0.85 | 42.5 | 9.1 | 54.3 | 0.190 |

| Etching | 12.8 | 0.52 | 38.7 | 8.7 | 52.1 | 0.190 |

| Deposition | 14.5 | 0.38 | 55.2 | 10.2 | 57.8 | 0.148 |

| CMP | 10.5 | 1.12 | 25.8 | 8.3 | 51.2 | 0.254 |

The CMP stage has the smallest gain margin (8.3dB) due to its high process gain (K_p = 0.25) and short time constant (tau_p = 30s), which makes the feedback loop more aggressive. Despite being the tightest margin, it still exceeds the 8dB minimum requirement.

9.4 Simulation Results

We simulate the five-stage cascade over a 24-hour production run with the following disturbance scenario:

• t = 0: Production starts with nominal material lot
• t = 2h: Material lot change at Stage 1 (step disturbance, w_0 = 0.008)
• t = 4h: Stage 2 etch rate drift begins (ramp disturbance, r = 0.0008/hr)
• t = 6h: Environmental temperature cycle causes Stage 3 deposition variation (sinusoidal, A = 0.005, period = 60s)
• t = 10h: Stage 4 CMP pad change (step disturbance, w_0 = 0.010)
• t = 14h: Combined disturbance -- simultaneous material lot change at Stage 1 and CMP pad wear ramp
• t = 20h: All disturbances active simultaneously (worst case)

9.5 Key Results

Defect containment: Over the 24-hour run, the 4-stage cascade (with active controllers at Stages 1-4 and metrology feedback at Stage 5) achieves the following defect containment rates:

| Stage | Out-of-tolerance events | Events contained by gate | Containment rate |

|---|---|---|---|

| Lithography | 847 | 793 | 93.6% |

| Etching | 612 | 581 | 94.9% |

| Deposition | 523 | 498 | 95.2% |

| CMP | 1,034 | 982 | 95.0% |

| Total | 3,016 | 2,854 | 94.7% |

The overall containment rate of 94.7% means that of all out-of-tolerance conditions detected during the 24-hour run, the PID gate controllers corrected 94.7% before the defect propagated to the next stage. The remaining 5.3% required discrete gate escalation (lot hold, recipe change, or human review).

Gate response time: The mean gate response time (from disturbance onset to corrective action initiation) across all stages is 178ms, with a 95th percentile of 312ms. This is dominated by the measurement latency (inline metrology sampling rate) rather than the controller computation time (which is less than 1ms).

Cascade attenuation: Measuring the defect rate at the output of each stage during the worst-case combined disturbance period (t = 20h):

| Measurement point | Defect rate |

|---|---|

| Stage 1 output | 0.41% |

| Stage 2 output | 0.049% |

| Stage 3 output | 0.0059% |

| Stage 4 output | 0.00071% |

The attenuation factors between stages are: Stage 1->2: 0.12x, Stage 2->3: 0.12x, Stage 3->4: 0.12x. This confirms the theoretical geometric attenuation of 0.12x per stage derived in Section 7.3. After four active stages, the raw material defect is attenuated by a factor of 0.12^4 = 2.07 x 10^-4.

Stability margins under disturbance: During the worst-case combined disturbance period, the minimum gain margins across all stages are:

| Stage | Nominal GM (dB) | Minimum GM under disturbance (dB) | Margin preserved |

|---|---|---|---|

| Lithography | 9.1 | 8.6 | 94.5% |

| Etching | 8.7 | 8.3 | 95.4% |

| Deposition | 10.2 | 9.5 | 93.1% |

| CMP | 8.3 | 8.0 | 96.4% |

All stages maintain gain margins above 8.0dB even under worst-case disturbance, confirming the robustness of the controller design.

9.6 Escalation Analysis

During the 24-hour run, the discrete gate mode activated for the following reasons:

| Trigger | Count | Mean resolution time | Resolved by |

|---|---|---|---|

| Defect exceedance | 89 | 4.2 min | Automatic recipe adjust (62), Human (27) |

| Control saturation | 34 | 8.7 min | Tool maintenance (21), Human (13) |

| Oscillation detection | 7 | 12.3 min | Controller retune (5), Human (2) |

| Model divergence | 32 | 6.1 min | Online re-identification (24), Human (8) |

| Total | 162 | 6.4 min | Auto: 112 (69.1%), Human: 50 (30.9%) |

The human intervention rate of 30.9% aligns with the MARIA OS recommended H=30% ratio from the fail-closed gate framework. The mean resolution time of 6.4 minutes is well within the SLA for semiconductor manufacturing quality escalations.

10. Benchmarks

We compare the control-theoretic quality gate against three baseline approaches across the semiconductor case study.

10.1 Comparison Conditions

• Baseline 1 -- No gate (open-loop): AI process controller operates without quality gates. Defects are detected only at final metrology inspection.
• Baseline 2 -- SPC-only gate: Standard Statistical Process Control with Western Electric rules. Gate activates (triggers lot hold) when SPC chart signals out-of-control condition. No continuous feedback control.
• Baseline 3 -- Threshold gate: Simple threshold-based gate. Gate activates when defect rate exceeds a fixed threshold. No PID control, no stability analysis.
• Proposed -- PID gate controller: Full control-theoretic gate with PID controller, anti-windup, derivative filtering, cascade inter-stage communication, and MARIA OS integration.

10.2 Benchmark Results

| Metric | No Gate | SPC-Only | Threshold | PID Gate |

|---|---|---|---|---|

| Defect containment rate | 0% | 67.2% | 78.4% | 94.7% |

| Mean detection latency | N/A | 12.4 min | 45s | 178ms |

| False alarm rate | N/A | 4.8% | 8.2% | 1.3% |

| Defect propagation (5 stages) | 100% | 41.2% | 28.7% | 0.021% |

| Stability guarantee | None | None | None | BIBO proven |

| Worst-case defect bound | Unbounded | Unbounded | d_max (no proof) | 0.101% (proven) |

| Gain margin | N/A | N/A | N/A | > 8dB |

| Phase margin | N/A | N/A | N/A | > 50 deg |

| Human escalation rate | 0% | 45.2% | 31.8% | 30.9% |

| Mean gate response time | N/A | 12.4 min | 45s | 178ms |

| Cascade attenuation | 1.0x (none) | 0.63x/stage | 0.52x/stage | 0.12x/stage |

10.3 Analysis

Detection speed: The PID gate controller provides a 4,000x improvement in detection latency over SPC (178ms vs. 12.4 minutes) and a 250x improvement over simple thresholding (178ms vs. 45s). This is because the PID controller acts on every measurement sample rather than waiting for a statistical trend to accumulate.

Containment effectiveness: The 94.7% containment rate represents a 41% improvement over SPC (67.2%) and a 21% improvement over thresholding (78.4%). The improvement comes from the controller's ability to correct defects proactively rather than merely detecting them.

Cascade performance: The most dramatic difference is in multi-stage defect propagation. After 5 stages, the PID gate allows only 0.021% of defects to propagate through the entire cascade, compared to 28.7% for thresholding and 41.2% for SPC. This is the power of geometric attenuation (0.12x per stage) versus linear attenuation.

Formal guarantees: The PID gate is the only approach that provides formal stability guarantees (BIBO stability, proven gain and phase margins, worst-case defect bounds). The other approaches provide empirical performance without provable bounds, leaving the organization exposed to worst-case scenarios that fall outside their historical experience.

False alarm rate: The PID gate has the lowest false alarm rate (1.3%) because it distinguishes between noise and real disturbances through the derivative filter and anti-windup mechanisms. SPC has a moderate false alarm rate (4.8%) determined by the control limits (typically set at 3-sigma). Simple thresholding has the highest false alarm rate (8.2%) because it triggers on any exceedance regardless of whether the exceedance is transient or sustained.

11. Future Directions

11.1 Adaptive PID Tuning

The PID gains derived in Section 5.4 assume known process parameters (K_p, tau_p). In practice, these parameters drift over time as equipment ages and processes evolve. An adaptive PID controller that continuously estimates the process parameters and re-tunes the gains in real time would maintain optimal performance without manual recalibration.

The adaptation law can be derived from Model Reference Adaptive Control (MRAC) theory. The process parameter estimates are updated using the error between the actual defect rate and the defect rate predicted by the reference model:

where gamma_1, gamma_2 > 0 are adaptation rates. The PID gains are then recomputed from the updated parameter estimates using the tuning rules of Section 5.4. Lyapunov stability of the adaptive system can be proven using a combined Lyapunov function that includes both the tracking error and the parameter estimation error.

11.2 Multi-Variable Control

Real manufacturing processes have multiple controllable inputs and multiple quality outputs. A single PID loop controlling defect rate via one process parameter is a simplification. Multi-variable control (e.g., Model Predictive Control / MPC) can handle the full input-output coupling and optimize multiple quality metrics simultaneously.

The extension to MPC within the MARIA OS framework replaces the PID controller C(s) with an optimization-based controller that solves at each time step:

where Q and R are weighting matrices, A and B are the discrete-time state space matrices, and the constraints enforce actuator limits. MPC naturally handles multi-variable coupling, constraints, and can incorporate preview information (e.g., known upcoming material lot changes).

11.3 Reinforcement Learning Integration

The PID controller provides provable stability guarantees but may not achieve globally optimal performance because it is a linear controller applied to a nonlinear process. Reinforcement Learning (RL) can discover nonlinear control policies that outperform PID in specific operating regimes.

The challenge is maintaining the stability guarantees that RL alone cannot provide. A hybrid architecture is promising: the PID controller serves as the safety-critical baseline, and an RL agent proposes modifications to the PID setpoints or gains. The MARIA OS gate engine evaluates each RL proposal against the Lyapunov stability conditions before permitting it. If the proposed modification would violate the stability conditions, the gate rejects it and falls back to the baseline PID.

This hybrid RL-PID architecture maps naturally to the MARIA OS dual-mode gate operation described in Section 8.1: the PID runs in continuous mode, the RL proposals go through the discrete gate, and the Lyapunov conditions serve as the risk scoring function.

11.4 Digital Twin Integration

A digital twin of the manufacturing process provides a simulation environment for testing controller changes before deploying them to the physical process. In the MARIA OS framework, the digital twin serves as an evidence source for the gate's evidence bundle. Before a controller gain change is approved (either by the adaptive algorithm or by a human engineer), it is first tested on the digital twin. The simulation results -- stability margins, transient response, disturbance rejection -- become part of the evidence bundle that the gate evaluates.

11.5 Cross-Fab Learning

Multiple fabrication facilities producing the same product type encounter similar disturbance profiles. Cross-fab federated learning of controller parameters could improve tuning convergence at new or recently reconfigured fabs. The MARIA OS Galaxy-level coordination (across tenants) and Universe-level coordination (across fabs within a company) provide the architectural scaffolding for federated parameter sharing.

Privacy-preserving techniques (differential privacy, secure aggregation) ensure that proprietary process data is not exposed during cross-fab learning. The shared artifacts are controller gains and disturbance statistics, not raw process data.

12. Conclusion

This paper has presented a control-theoretic framework for manufacturing quality gates that transforms the gate from a passive checkpoint into an active feedback controller. The key contributions are:

Defect rate as state variable. By modeling the defect rate d(t) as a continuous dynamical variable governed by a first-order LTI system, we bring the full apparatus of control theory to bear on the quality gate design problem. The plant transfer function G_p(s) = K_p / (tau_p s + 1) characterizes the process dynamics, and the disturbance transfer function G_w(s) characterizes the impact of material variation, tool wear, and environmental drift.

Lyapunov stability guarantee. We derive explicit conditions on the PID controller gains (K_P > 0, K_D bounded above, K_I bounded above) that guarantee global asymptotic stability of the quality gate closed-loop system. The Lyapunov function V(x) = (1/2) e^2 + (1/2) K_I (integral of e)^2 provides a constructive proof that the defect rate converges to target for any initial condition.

PID gate controller with industrial features. The controller design includes anti-windup (back-calculation), derivative filtering, and explicit gain tuning rules parameterized by settling time, damping ratio, disturbance rejection requirement, and stability margin targets. The design produces controllers with GM > 8dB and PM > 50 degrees, exceeding industrial standards.

Disturbance rejection analysis. We classify manufacturing disturbances into three types (step/material, ramp/tool wear, sinusoidal/environmental) and prove that the PID controller rejects step disturbances to zero steady-state error, bounds ramp disturbance error to r tau_p / (K_p K_I), and attenuates sinusoidal disturbances by the sensitivity function magnitude. The BIBO stability theorem provides a hard upper bound on the defect rate for any bounded disturbance.

Multi-stage cascade analysis. We derive the cascade transfer function for M sequential quality gates and show that properly tuned gates provide geometric attenuation of 0.12x per stage, reducing defect propagation by a factor of 2 x 10^-4 through a 5-stage cascade.

Semiconductor case study. The framework is validated on a 5-stage semiconductor fabrication process over a 24-hour production run with realistic disturbance profiles. The PID gate controller achieves 94.7% defect containment, 178ms mean gate response time, and maintains gain margins above 8dB throughout, including during worst-case combined disturbance scenarios.

MARIA OS integration. The control-theoretic gate operates as a dual-mode extension of the MARIA OS Responsibility Gate Engine, combining continuous PID control with discrete fail-closed gating. The integration leverages the MARIA Coordinate System for hierarchical configuration, the Decision Pipeline for audit-complete escalation, and the evidence bundle framework for manufacturing-specific process data.

The broader implication is that quality governance in manufacturing is a control problem, not a classification problem. Traditional quality gates ask 'is this product defective?' The control-theoretic gate asks 'is the defect rate stable, and what corrective action maintains stability?' This shift from reactive detection to proactive stabilization is the foundation for AI-driven manufacturing that is both autonomous and governable.

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